PIC18F4450T-I/ML【PDF 120/241 页】IC PIC MCU FLASH 8KX16 44QFN

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206

XMEGA A [MANUAL]

8077I–AVR–11/2012

response. The addressed device signals ACK by pulling the SCL line low during the ninth clock cycle, and signals NACK

by leaving the line SCL high.

19.3.4 Address Packet

After the START condition, a 7-bit address followed by a read/write (R/W) bit is sent. This is always transmitted by the

master. A slave recognizing its address will ACK the address by pulling the data line low for the next SCL cycle, while all

other slaves should keep the TWI lines released and wait for the next START and address. The address, R/W bit, and

acknowledge bit combined is the address packet. Only one address packet for each START condition is allowed, also

when 10-bit addressing is used.

The R/W bit specifies the direction of the transaction. If the R/W bit is low, it indicates a master write transaction, and the

master will transmit its data after the slave has acknowledged its address. If the R/W bit is high, it indicates a master read

transaction, and the slave will transmit its data after acknowledging its address.

19.3.5 Data Packet

An address packet is followed by one or more data packets. All data packets are nine bits long, consisting of one data

byte and an acknowledge bit. The direction bit in the previous address packet determines the direction in which the data

are transferred.

19.3.6 Transaction

A transaction is the complete transfer from a START to a STOP condition, including any repeated START conditions in

between. The TWI standard defines three fundamental transaction modes: Master write, master read, and a combined

transaction.

Figure 19-5 on page 206 illustrates the master write transaction. The master initiates the transaction by issuing a START

condition (S) followed by an address packet with the direction bit set to zero (ADDRESS+W).

Figure 19-5. Master write transaction.

Assuming the slave acknowledges the address, the master can start transmitting data (DATA) and the slave will ACK or

NACK (A/A) each byte. If no data packets are to be transmitted, the master terminates the transaction by issuing a STOP

condition (P) directly after the address packet. There are no limitations to the number of data packets that can be

transferred. If the slave signals a NACK to the data, the master must assume that the slave cannot receive any more

data and terminate the transaction.

Figure 19-6 on page 207 illustrates the master read transaction. The master initiates the transaction by issuing a START

condition followed by an address packet with the direction bit set to one (ADDRESS+R). The addressed slave must

acknowledge the address for the master to be allowed to continue the transaction.

A/A

ADDRESS

DATA

Address Packet

Data Packet

Transaction

N data packets

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